Abdullah, Isam, Macdonald, J Emyr ![]() ![]() |
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Abstract
We report the effect of bias stress on the drain current and threshold voltage of n-channel thin-film transistors based on solution processed In2O3 layers. Application of a positive gate bias for variable time-periods led to displacements of the transfer curves in the positive gate bias direction. On switching off the gate bias, the transfer curves returned close to their pre-stress state on a timescale similar to that when the gate bias was switched on. The time dependence of the threshold voltage shift is described well by a stretched-exponential model. The temporal behaviour of the threshold voltage shifts is consistent with charge trapping as the dominant effect, although some defect formation cannot be ruled out.
Item Type: | Article |
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Date Type: | Publication |
Status: | Published |
Schools: | Physics and Astronomy |
Additional Information: | Original content fromthis work may be usedunder the terms of theCreative CommonsAttribution 4.0 licence.Any further distributionof this work mustmaintain attribution tothe author(s) and the titleof the work, journalcitation and DOI. |
Publisher: | IOP Press |
ISSN: | 2515-7639 |
Date of First Compliant Deposit: | 26 October 2020 |
Date of Acceptance: | 29 October 2020 |
Last Modified: | 05 May 2023 03:13 |
URI: | https://orca.cardiff.ac.uk/id/eprint/135927 |
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