Motor Overvoltage Mitigation Using SiC-Based Zero-Voltage Switching Inverter

The motor overvoltage phenomenon is an issue that may arise from the high voltage slew rates (<inline-formula><tex-math notation="LaTeX">$\mathrm{d}v/\mathrm{d}t$</tex-math></inline-formula>) of silicon carbide <sc>mosfet</sc>s in cable-fed drives. This can lead to substantial strain on cable and motor insulation, resulting from partial discharges and uneven voltage distribution. In line with this, this article presents a novel method to select inductor and capacitor parameters for a zero-voltage switching (ZVS) inverter to mitigate motor overvoltage. The ZVS inverter employs only one additional active switch on the positive dc terminal compared with two-level inverters. This prevents the need for bulky <italic>LCR</italic> and <italic>RC</italic> passive filters or multilevel inverters in conventional solutions, which may lead to increased volume and losses. The presented approach suppresses overvoltage oscillations by profiling the <inline-formula><tex-math notation="LaTeX">$\mathrm{d}v/\mathrm{d}t$</tex-math></inline-formula> of both resonant and natural commutations while minimizing the switching losses. A comparison with alternative techniques for mitigating motor overvoltage was conducted to demonstrate the method's efficacy, including two-level passive filter strategies and three-level inverters. The presented technique was validated through simulations in PLECS and MATLAB/Simulink, demonstrating a 1% increase in efficiency and a 30% reduction in volume. Furthermore, the method was experimentally verified, showing the measured overvoltage being reduced from 2 to 1.06 per unit.

. The overvoltage phenomenon, also known as the reflective wave phenomenon, occurs due to an impedance mismatch between the cable and motor, leading to the reflection of voltage pulses generated by the inverter [5], [6].The severity of this phenomenon is influenced by the rise time of voltage pulses, cable characteristics, and cable length [7], [8].
Incorporating long cables to connect a SiC MOSFET inverter with a motor has the potential to generate a motor terminal voltage twice the magnitude of the inverter voltage, resulting in recurring partial discharges and rapid insulation breakdown [9], [10].This predicament is particularly evident at high switching frequencies [11], [12].Based on standard IEC 60034-18-41 [13], the first two coils of a motor encounter 40% of the voltage when the rise time is approximately 200 ns.Thus, it is critical to comprehend the relationship between voltage rise time and cable length and to formulate countermeasures for high-speed, high-power-density motors with low insulation thickness [14], [15].
The conventional approach to mitigate overvoltage is to use LCR filters at the inverter terminal to limit the dv/dt of pulsewidth modulation (PWM) pulses or RC filters at the motor terminals to match the impedance of the cable and motor [16], [17], [18], [19].This approach is simple and effective, but it has some drawbacks, such as the need for bulky LCR passive components, which occupy a large volume and subsequently increase the power loss and cost [11].Moreover, there is an increased difficulty in adjusting the filter parameters when there are changes in the drive system voltage and power requirements [20].In addition, the high dv/dt of SiC MOSFETs may interact with the filter parasitic elements, resulting in a highfrequency impedance mismatch, increasing, in turn, the motor overvoltage [17].
Filter-less strategies for addressing the issue of motor overvoltage have been proposed in the literature [20] and [21], such as utilizing a three-level neutral point clamped inverter to decrease voltage fluctuations or a quasi-three-level (Q3L) T-type inverter to cancel and mitigate voltage reflections.However, an overvoltage of 1.2 per unit (p.u.) remains despite introducing such topologies [22].An alternative approach that aims to fully mitigate overvoltage is the implementation of a soft-switching inverter and profiling the dv/dt.This technique actively determines the dv/dt of voltage transients.An example of this approach is the soft-switching auxiliary resonant commutated pole inverter presented in [23].Regardless, these three-level topologies may not be practical for three-phase systems due to the high number of switching devices required, volume 0885-8993 © 2023 IEEE.Personal use is permitted, but republication/redistribution requires IEEE permission.
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constraints, and initial capital costs.Using active gate drivers may also be an effective technique, but they are costly and add complexity to the system.Furthermore, their application may be limited in specific systems due to design constraints, such as the need for high current drive capability [24].Generally, cable-fed motor drive systems are required in inhospitable and inaccessible environments where the inverter and motor are connected at different locations [25].The challenge of effectively mitigating motor overvoltage in these extreme conditions while maintaining high efficiency and minimizing volume and cost remains an ongoing research topic.To this end, this article presents a novel approach to addressing this issue by utilizing a zero-voltage switching (ZVS) inverter.Most ZVS topologies presented in the literature require several additional active switches for three-phase systems, which may not be suitable for cable-fed systems due to volume constraints in these conditions.For this reason, the topology presented in [26] is utilized in this article, since only one additional active switch is required.To realize ZVS without requiring multiple active switches, two types of commutation are devised, namely, resonant and natural commutations.Moreover, by incorporating ZVS and a modified space vector PWM (SVPWM) scheme, the switching losses, electromagnetic interference, and power density are improved without significantly compromising the general structure of the two-level topology [27].
Prior research on the adopted ZVS topology has focused on grid-connected and photovoltaic inverters [27], [28].In addition, the changes in dv/dt that occur during resonance and natural commutations are not uniform [29].Thus, any attempt to characterize dv/dt for resonant commutations may lead to discrepancies in the value of dv/dt observed during natural commutations.Hence, it is necessary to take extra timing considerations into account to prevent motor overvoltage at each switching transition consistently.Furthermore, failure to address this issue adequately may still result in repetitive partial discharges at either resonant or natural commutations and prompt motor insulation failure.Further research is therefore necessary to explore the implementation and design parameters of the ZVS inverter for motor drives and overvoltage mitigation, specifically in the context of cable-fed systems.
The work presented in this article makes three critical contributions to the field of motor drive systems.First, it adapts the ZVS inverter topology presented originally in [26] to eliminate motor overvoltage in cable-fed drive systems while only requiring one auxiliary circuit.Second, an in-depth analysis of the inverter parameters based on different cable lengths and characteristics is conducted, which is crucial for the scalability and applicability of the ZVS topology for overvoltage mitigation.Finally, a comprehensive comparison of the volume and efficiency of the ZVS inverter with existing solutions is presented, including LCR and RC passive filter methods and three-level inverters, highlighting the advantages of the ZVS topology.
The effectiveness of the proposed approach was evaluated using the simulation tools MATLAB/Simulink and PLECS (Plexim) and experimentally validated with a 1.23 kW ac Fig. 1.Three-phase ZVS inverter cable-fed motor drive system.permanent magnet brushless servo motor drive system.It is shown that the presented method can improve the adaptability of the ZVS inverter for motor drive systems as follows: 1) To achieve full overvoltage mitigation, guidelines are shown for selecting the values of resonant capacitors and inductors based on the cable characteristics, length and dv/dt requirements.By suitably designing the resonant parameters, the rise time of both resonant and natural commutations can be profiled-thereby, mitigating motor overvoltage.2) In order to reduce the switching turn-OFF losses in the ZVS inverter, the duration of the voltage rise time has been prolonged.Ordinarily, increasing the voltage rise time in hard-switching inverters leads to larger switching losses.Nonetheless, as detailed in this article, it is feasible to curtail the turn-OFF losses in the ZVS inverter.Given that ZVS already provides negligible switching turn-ON losses, the presented approach enhances the efficiency of the entire motor drive system.The previous factors make the solution promising for addressing the issues of the reflective wave phenomenon in cable-fed drive systems and mitigating motor overvoltage while having minimum impact on the volume and efficiency of the whole drive system.

II. REVIEW OF ZVS TOPOLOGIES
The three-phase ZVS inverter and the cable-fed motor are shown in Fig. 1.The auxiliary circuit is connected in series with the positive terminal of the inverter.A brief introduction to the control of the ZVS inverter is presented in this section.

A. Topology and Principle of Operation
Fig. 2 shows two types of current commutation in the legs of the ZVS inverter at a positive phase current i m .In Case I, when switch S + is turned-OFF, i m transitions from S + to the lower antiparallel diode with the assistance of the paralleled capacitor C r .During this transition, the ZVS is achieved, and dv/dt is controlled by varying C r .Conversely, Case II shows that the current transitions from the lower antiparallel diode D − to S + , bypassing C r , before S + is activated.This results in hard switching and an increase in switching losses.
To enable ZVS during switching transitions in Case II, an auxiliary switch, S 7 , and clamping capacitor C c are utilized.S 7 predominantly conducts during the operating cycle, thereby accumulating energy in C c .In anticipation of the occurrence of Case II transitions, it is necessary for the bus voltage V bus subsequent to the auxiliary branch to resonate towards zero via the deactivation of S 7 .Hence, in a conventional modulation scheme the switching frequency of S 7 will be high since Case II commutations will occur multiple times within each switching cycle.
In three-phase systems, the switching losses and complexity of the inverter control can be reduced by synchronizing the switching of S 7 with the main switches in each phase leg.If SVPWM is used as the modulation technique [30], this can be accomplished by modifying the vector states based on current polarity.Sector I can be subdivided into two subsectors, Sectors I-I and I-II, as shown in Fig. 3.Each sector has a designated vector sequence of the switching states 000, 111, 100, and 110.For instance, in Sector I-I, the arranged vector sequence is 111-100-110-111, where S 1 is always conducting and S 3 and S 5 are synchronized from the zero vector to the first vector.This method requires only one transition of S 7 per PWM cycle to achieve ZVS in Case II.

B. Analysis of Operation Modes
The steady-state operation of the inverter is shown in Fig. 4 and is divided into six distinct stages of operation for Sector I-I [27].These are described next.
Stage 1 (t 0 − t 1 ).Initial Stage: The circuit is in state vector V7 (111) with S 1 , D 3 , and D 5 in conducting state.In the auxiliary circuit, S 7 is in conducting state and the resonant inductor (L r ) is charged by C c .The size of C c is large enough that the voltage across it is constant during a switching cycle.The current across the auxiliary switch is i S7 = −I Lr and V bus = V dc + V Cc .The equivalent circuit of the initial stage is shown in Fig. 5(a).
Stage 2 (t 1 − t 2 ).First Resonance: When S 7 is turned-OFF, L r discharges the parallel capacitors C 4 , C 6 , and C 2 and resonates V bus to zero.The time duration for this resonance corresponds to the resonant fall time t fr .As the circuit is no longer in state vector V7 (111), L r resonates the voltage across S 7 to V dc + V Cc with I Lr remaining negative.The equivalent circuit of this stage is shown in Fig. 5(b).
Stage 3 (t 2 − t 4 ).Freewheeling Diodes: After the first resonance, L r still has residual energy to keep I Lr negative.Freewheeling body diodes D 4 , D 6 , and D 2 begin to conduct and ZVS is realized for S 6 and S 2 .The resonant inductor current I Lr reaches zero at t 3 and the freewheeling diodes are turned-OFF.The motor currents at phase b (i b ) and phase c (i c ) now commutate the diodes D 3 and D 5 to S 6 and S 2 .I Lr is now equivalent to i b + i c at t 4 .The equivalent circuit for this scenario is shown in Fig. 5(c).Stage 4 (t 4 − t 5 ).Short Circuit: At t 4 , all six main switches are turned-ON, entering the short-circuit mode.During this stage, L r stores energy for the ZVS turn-ON of S 7 .This results in I Lr increasing linearly by the boost current i boost , whereas the voltage V Lr across the inductor is clamped to V dc , which is necessary for achieving ZVS.The equivalent circuit for this scenario is shown in Fig. 5(d).
Stage 5 (t 5 − t 6 ).Second Resonance: At t 5 , S 4 , S 3 , and S 5 are turned-OFF, and the energy stored in L r discharges V Cc , resonating C 4 , C 3 , C 5 , and C 7 .The time duration for this resonance corresponds to the resonant rise time t rr .This stage ends when S 7 is turned-ON under ZVS conditions.The equivalent circuit for this scenario is shown in Fig. 5(e).
Stage 6 (t 7 /t 8 ).Case I Commutation: At t 7 , S 6 is turned-OFF and i b initiates the charging of C 6 .Subsequently, C 3 is discharged as S 3 is turned-ON.Following the buffer of the resonant capacitor, ZVS is achieved.Similarly at time t 8 , S 2 is turned-OFF and S 5 is turned-ON through the parallel capacitors, as shown in Fig. 2(a).The time required for charging and discharging of parallel capacitors is given by the natural rise and fall time t n .The equivalent circuit corresponding to this process at time t 7 is shown in Fig. 5(f).Following this stage, the inverter returns to Stage 1 of a new vector switching cycle.

III. RESONANT PARAMETER DESIGN
Following an overview into the control of the inverter, it has been established that ZVS is possible through the resonant action of L r and C r .The selection of these parameters has been discussed in the literature [29].Also, the principle of actively profiling dv/dt to not excite cable antiresonance has been extensively discussed [23].However, in the ZVS inverter, the rise and fall times of the resonant stages (Stages 2 and 5) and natural commutation (Stage 6) are not the same value, i.e., Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
t rr = t fr = t n .To address this, the selection of L r and C r to profile dv/dt at each type of commutation of the ZVS inverter so as to mitigate motor overvoltage is discussed next.

A. Selection of the Resonant Inductor L r
The resonant inductor is designed to charge and discharge the resonant capacitors in the resonant stages by storing energy.From this viewpoint, the inductance should be as large as possible.However, it is preferable to limit its value to reduce capital costs, inverter losses, and volume.During the resonant stages, the maximum dv/dt of the main switches is analyzed using Kirchhoff's voltage law [29] as follows: whereby m i is the modulation index and i m_ max is the maximum motor phase current.The resonant fall voltage is denoted as v fr and the resonant rise voltage as v rr .Assuming that all the parallel resonant capacitors have the same capacitance value, i.e., , where C oss is the output capacitance (for this article, the value for the SiC MOSFET Wolfspeed C2M0080120D is used, with a value of 92 pF [31]).
Since the maximum voltage across the main switches is V dc + V Cc , and assuming the rise times of both resonant commutations are not the same value, using (1), L r based on the falling commutations is designed using the follows: ( The resonant inductance can also be determined by the rising commutations; however, as later described in Section III-C, only the falling commutations are required for this.

B. Selection of the Resonant Capacitor C r
During natural commutation in Case I, the appropriate configuration of the corresponding voltage slew rate dv n /dt is dependent on the charging and discharging characteristics of C r at each main switch.Fig. 4 shows that the drain-source voltage V ds fluctuates in response to the charging and discharging rate of C r .Evaluation of dv n /dt across each main switch is conducted using Kirchhoff's first law as follows: whereby the sign changes represent the charging and discharging of the resonant capacitors.Since the SVPWM has been modified to allow for two concurrent commutations, the maximum motor current is √ 3 2 i m_ max with respect to the conventional SVPWM [29].The natural commutation voltage slew rates using i m_ max are found as follows: With the specified rising times t n and the maximum phase current of the modified space vector, C r is determined from (5) as follows:

C. Design Procedure for Overvoltage Mitigation
The relationship between motor overvoltage and the propagation delay t p is shown in Fig. 6 with t p given as a function of cable length l [32] as follows: whereby L cab is the cable inductance and C cab is the cable capacitance.These parameters are experimentally determined using a precision LCR meter [33] or measured directly as shown in Section V.It is important to note that (7) assumes a lossless cable and factors such as cable resistance can have a slight indirect effect on t p , particularly at high frequencies.Therefore, accurate simulation modeling of the cable, as mentioned in Section IV, is crucial.It is observed from Fig. 6 that the overvoltage oscillations can effectively be suppressed by designing the rise times to 4t p , with t p being determined by the specific cable length and its inherent characteristics.As shown in Fig. 6(d), the motor voltages V m no longer fully neutralize one another at 5t p , resulting in an overvoltage despite the longer rise time.Thus, complete suppression of V m occurs when the inverter voltage V i does not excite the cable antiresonance, and where a ∈ Z + .This phenomenon is explained by the superposition principle, where V i is divided into two equal pulses with a temporal time displacement of 2t p .Given the assumption of unity reflection coefficients [18], both inverter voltages are reflected at twice the magnitude at the motor terminals.Due to the time displacement, the resultant motor voltages cancel each other at 4at p [23].
To ensure consistent suppression of overvoltage in the ZVS inverter, the rise and fall times at each resonant and natural commutation must be carefully selected.As noticed from ( 1) and ( 2), the values of dv/dt can not be equal without restricting V dc or i m_ max , such that To this extent, the resonant rise dv rr_ max /dt from ( 2) is denoted as a function of the resonant fall dv fr_ max /dt from (1) and the natural dv n /dt from (5) with a modulation index 0.4 ≤ m i ≤ 0.8 as follows: From (10), it is observed that the dv/dt can be profiled by carefully selecting the rise time at each commutation.This is possible since the change in PWM voltage magnitude at each commutation has the same value (i.e., V dc + V Cc ).The rise time selection for each dv/dt is mathematically expressed as follows: To ensure effective overvoltage suppression, it is imperative first to establish C r as given in (6) utilizing t n = 8t p .Subsequently, L r can be calculated using the established capacitance and inductance from (3).Finally, t fr should be set to 4t p .As per (1), by setting a constraint on the maximum rise time, this will enable t rr to be equal to 8t p .By following this methodology, complete overvoltage suppression can be achieved at both the resonant and natural rise times.A diagram outlining this process is shown in Fig. 7.

D. Voltage and Current Stress on Main Switches
Assuming that all the parallel resonant capacitors are of the same value, the minimum i boost is expressed as [34] where the resonant impedance is defined as When the inverter is operating at steady state, the clamping capacitor voltage V Cc is defined by the volt-second balance principle of the resonant inductor as follows: whereby d o is the turn-OFF duty cycle of S 7 .Since the voltage across the main switches is V dc + V Cc , to avoid high voltage stress, d o should be less than 0.1 [34].
The current I Lr of the resonant inductor [27] is given by the following expression: When calculating the resonant parameters for a system, it is essential to consider the value of Z r to prevent excessive current stress on the power switches.The current stress at the auxiliary switch (i m + I L r ) and main switches (i m + i boost /3) is calculated using (12) and (14).Since the current stress can be limited by increasing the value of Z r [27], the design for overvoltage mitigation must consider Z r or increase the current rating of the auxiliary and main switches.One way to accomplish this is to increase the value of L r with respect to C r .Specifically, Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.a different set of resonant rise and fall time requirements can be chosen as long as t r in ( 8) is met for all natural and resonant commutations.Adherence to this condition ensures that the voltage does not cause excitation of the cable antiresonance.Neglecting the influence of Z r may give rise to MOSFET malfunctioning, particularly in extended utilization periods, potentially incurring higher expenses in maintenance and replacement.

E. Volume Considerations
The volume of the primary components in the ZVS inverter is shown in Fig. 8.A comparison between a conventional two-level inverter with a passive LCR filter, RC filter, and a conventional three-level inverter is also shown.The selection of passive components was based on the system specifications, which included the dv/dt requirements for a 1.23 kW ac permanent magnet brushless servo motor operating at a switching frequency of 20 kHz and a dc voltage of 300 V.
The sizing of the heat sink, influenced by natural air convection, relies on calculating the thermal resistance of the heat sink.This calculation incorporates the simulated power losses, as computed in Section IV-B, along with the heat sink temperature obtained from PLECS simulations.For these computations, an ambient temperature of 40 °C was considered [35].Subsequently, the heat sink volume can be determined, as discussed in [36].This process involves employing curve fitting techniques to establish a correlation between the volume of various extruded heat sinks and their corresponding heat sink thermal resistances.In addition, for all active switches, the packaged DYNATRON heat sink and cooling fan (Part No. G199) [37] are employed to ensure effective heat dissipation.
The ZVS inverter and the two-level inverter with LCR filter utilizes ferrite leaded inductors from Würth Elektronik [38], whereas the two-level filter inverters use low-inductive 100 Ω resistors from Ohmite [39].In addition, 10 nF polypropylene film capacitors from Panasonic [40] are utilized in both the ZVS inverter and passive filters.The volume of each component was determined based on the dimensions specified in their respective datasheets.Only basic LCR and RC passive filters were implemented in this study; however, comprehensive information on more advanced filters is available in the literature [16].
The ZVS inverter exhibits a volumetric reduction of ≈30% compared with the three-level inverter and ≈40% reduction compared with the two-level inverter with an LCR and RC filter.It is also worth reminding that the LCR passive filter is typically installed at the inverter terminal, where the RC passive filter is installed at the motor terminal.Moreover, determining the size of C c in the ZVS inverter is contingent upon the dc voltage stipulations to provide a constant voltage across its terminals in a switching period.Therefore, its practicality can be impacted by the availability of suitable constituent elements.

IV. SIMULATION RESULTS
A simulation was carried out in MATLAB/Simulink to verify the effectiveness of the ZVS topology for overvoltage mitigation.A high-frequency ac cable and motor model was implemented from [33] to accurately model and predict the transient overvoltage oscillations.This cable model includes the impact of both the skin and proximity effects and the dielectric losses at high frequency range.A breakdown of the system parameters is given in Table I, which have been adopted for both software simulation and experimental testing.Experimental results are reported in Section V.

A. Overvoltage Mitigation Comparison
As shown in Section III-C, it is necessary to ascertain the optimal resonant and natural time t r for every cable length employed to address the issue of overvoltage.The propagation time t p for each cable length is given in Table II, alongside the calculated values of C r , L r , and Z r , which were obtained using the prescribed guidelines in Fig. 7.The values for C r and L r have been rounded to the nearest component commercially available.It is noticed that Z r remains approximately the same value despite increasing the cable length.This is due to the ratio of C r and L r being the same since only t p is varying.It is worth highlighting that these parameters were determined Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.based on the experimental dc voltage V dc = 300 V and i m_ max = 3 A. Changing these system parameters (i.e., load current) may slightly impact the motor overvoltage mitigation, as later shown in Section V-C.
The resonant rise and fall times for a single switching commutation are shown in Fig. 9(a).As outlined in (9), it is imperative that the fall rate of voltage be greater than the rising rate of voltage.Hence, the rise time t rr is chosen as 8t p , and the fall time t fr is chosen as 4t p .Utilizing a measured value of t p of 86.7 ns for a 20 m cable, the calculated resonant rise time and resonant fall time are 693.6 and 346.8 ns.Comparing these values with the simulated results reveals a disparity of ≈ 5%.Likewise, the natural commutations in Fig. 9(b) are designed to 8t p .Compared with the calculated rise times, a deviation of 1% results with regard to the simulated outcomes.These commutations are structured not to stimulate cable antiresonance, thereby mitigating overvoltage.
The performance of the ZVS topology was compared with the conventional two-level inverter with no passive dv/dt filters and the same system parameters.As shown in Fig. 10(a), the phase voltage V m of the two-level inverter has almost twice the value of the dc voltage V dc at 560 V.This would result in rapid insulation failure impacting the long-term reliability of the motor.An extended view in Fig. 10(b) shows that by using the ZVS topology with active dv/dt profiling, the motor overvoltage is fully mitigated to the inverter bus voltage V dc + V Cc at 345 V. Significantly, the voltage V i,ab between phases a and b of the ZVS inverter is equivalent to V dc + V Cc due to the presence of the clamping capacitor, thus enabling the motor overvoltage to subside to this increased voltage level.
It is worth noting that extended exposure to high temperatures or mechanical stress can lead to slight fluctuations in the values of C r , which can influence the predetermined rise and fall times, ultimately affecting overvoltage mitigation.Fig. 11 shows the simulated relationship between C r and V m for a 20 m cable, revealing that V m increases up to 1.14 p.u. when C r deviates from the optimal value of 2.64 nF.While variations in L r can Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 12. Simulated system efficiency of ZVS motor drive system compared with Q3L T-type inverter, two-level inverter with passive LCR and RC filter (t p = 86.7 ns, f sw = 20 kHz, and m i = 0.8.) also impact V m , its effect is less significant, particularly if L r does not deviate considerably from its ideal value.Moreover, these variations in L r only affect resonant commutations and not natural commutations.
Furthermore, passive components may undergo gradual aging effects over extended periods, contingent on factors, such as component quality, construction, and operating conditions.To mitigate the risks associated with aging phenomena, it is advisable to opt for components with appropriate tolerances and perform regular inspections and replacements.

B. Efficiency Comparison
The switching and conduction losses of the inverter were determined using PLECS based on parameters in the Wolfspeed C2M0080120D datasheet [31].This includes the internal gate resistance (R g−in ), external gate resistance (R g−ext ) and normally ON-state resistance (R ds(on) ).The gate drive voltage is set as −5/20 V during turn-OFF (V ggl ) and turn-ON (V ggh ).The critical parameters are extracted from datasheet and further given in Table I. using manufacturer data, multidimensional look-up tables were employed to accurately estimate and average the losses with case temperature T c = 40 °C.The system efficiency η sys was also calculated through software simulation using the following: where P in is the dc input power, P inv is the total inverter losses, P mot is the total motor losses, and P cable is the total cable losses.The efficiency of a drive system utilizing a Q3L T-type inverter and a two-level inverter with passive LCR and RC filters are compared in Fig. 12.The results show that the ZVS topology exhibits a higher system efficiency for all power ratings.The improved efficiency is primarily attributed to the reduced number of active switches compared with the three-level inverter, resulting in lower switching and conduction losses for the SiC Fig. 13.Power loss distribution comparison of two-level inverter with passive LCR and RC filter, Q3L T-type inverter, and ZVS inverter.P msw,on , P msw,off and P mcond are the turn-ON, turn-OFF switching losses and conduction loss of the main switches.P asw,off and P acond are the switching turn-OFF and conduction power loss of the auxiliary switch.P filter is the filter power loss.P m,Fe and P m,Cu are the motor iron and copper losses.The total power losses of the motor drive system are correspondingly 91.5, 88.2, 45.8, and 36.0W. (Simulation parameters: load torque T L = 4 Nm, rotor speed ω r = 3000 r/min, f sw = 20 kHz, and t p = 86.7 ns.) MOSFET inverter.However, the two-level inverter experiences substantial power losses due to the bulky LCR and RC filters and the hard-switching technique required, as shown at rated conditions in Fig. 13.Specifically, the switching turn-ON losses are evident in the hard-switching inverters, whereas in the ZVS inverter, these losses are absent.
Although the inverter analyzed in this study operates at a switching frequency of 20 kHz, at higher frequencies up to 300 kHz, the turn-ON losses would become the dominant source of loss in the system, as reported by previous literature [27].Furthermore, it should be noted that while the simulated comparison is performed at a dc link voltage of 300 V, the results can be extended to higher voltages with a similar outcome.When operating at higher voltages, the load currents are expected to increase, which, in turn, leads to higher losses in both the inverter topologies and passive filters.A relevant study in [26] conducted a comparable loss analysis between a hard switching two-level inverter and the ZVS inverter at 600 V.The findings from the study reaffirmed the superior efficiency of the ZVS inverter at higher voltages.
During a ZVS turn-OFF transition, the voltage gradually increases from zero while the current quickly drops.This results in the switching losses being reduced when compared with a hardswitching inverter.In the ZVS inverter, C r can systematically control the voltage slew rate.Therefore, by reducing the dv/dt, the switching turn-OFF losses P sw,off can be reduced [41].This is shown in Fig. 14, where P sw,off was calculated as the product of the MOSFET drain current i d and V ds .However, it is imperative to meticulously weigh the benefits and drawbacks of the preferred performance metrics at a high-switching frequency and the ideal efficiency to ascertain the most favourable voltage rise time for the ZVS inverter.
Although the ZVS inverter exhibits negligible switching turn-ON losses, an additional turn-OFF loss results from adding the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.short-circuit stage.Thus, comprehending the significance of P sw,off for slower dv/dt is crucial.By employing the propagation times associated with cable length, the correlation between voltage rise time 8t p , P sw,off , and η sys is listed at rated motor conditions in Table III.The 1 m cable was only used as a base comparison with no dv/dt profiling, as the overvoltage phenomenon does not occur at this cable length.

TABLE III TOTAL ZVS TURN-OFF POWER LOSS AT 20 KHZ
The primary factors contributing to power loss in ac cables are attributable to the dielectric and resistive phenomena, specifically the skin and proximity effects.It is important to note that as the system operates at higher switching frequencies and longer cable lengths, these losses become more significant and can greatly impact the overall system efficiency [42].In addition, copper and iron losses of L r have been accounted for; however, they are considered negligible at the current inverter ratings in this study.

V. EXPERIMENTAL RESULTS
To confirm the suitability of the presented ZVS parameter selection for mitigating motor overvoltage, a three-phase ZVS inverter is employed to deliver power to a motor via a range of long cables; 5, 10, 15, and 20 m, as shown in Fig. 15.In line with this configuration, a four-core unscreened 16 AWG cable from Lapp [43] was employed with the earth core grounded.This provides a return path for common-mode currents, reducing the EMI within the cable and minimizing interference with surrounding equipment and circuits.The motor rotor angle is measured by an incremental encoder and processed by the DSP (Xilinx Zynq 7030 SoC).The driving signals are generated from the DSP and sent to the gate drive circuit (Texas Instruments ISO5452-Q1).The gate driver controls the rise and fall times for the active SiC MOSFET power switches (C2M0080120D) with SiC Schottky diodes (C4D20120D).

A. Impact of Cable Length
By selectively adjusting the resonant parameters, it is possible to achieve the desired dv/dt for natural and resonant commutations as a function of cable length while conforming to (8), thereby mitigating motor overvoltage at each switching transition.The controlled dv/dt through the ZVS inverter is shown in Fig. 16 by utilizing the parameters outlined in Table II.As shown in Fig. 16(a) and (g), an increase in cable length results in a proportional increase in both natural commutation and resonant rise commutations, with a rise time of ≈ 8t p and resonant fall times of 4t p for each cable length.Upon comparison of the measured resonant fall times at a cable length of 20 m with the simulated value of 325 ns, a discrepancy of 7% is observed.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Similarly, the simulated resonant rise times are 662 ns, which exhibits a deviation of 4% when compared with the measured values.
Fig. 17 compares the differential-mode inverter voltage V i,ab between phases a and b with the motor overvoltage V m,ab when a 20 m cable is adopted.A hard-switching two-level inverter without a filter is used as a baseline for comparison by shortcircuiting the auxiliary branch and removing C r .The measured rise and fall times for the two-level inverter with no filter are 52 and 31 ns, correspondingly.As shown in Fig. 17(a), V m,ab can increase up to 2 p.u.If the motor and cable are not designed to withstand this voltage magnitude, the resulting overvoltage can exceed the partial discharge inception voltage of the rotor winding, leading to partial discharges that may significantly decrease the motor's operational lifespan.Thus, the motor voltage reflections persist until fully damped to the inverter PWM voltage.This effect depends on the ac skin resistance, proximity effects, and dielectric losses of the ac cable [33].In addition, the occurrence of high-frequency ac current ripple during switching transients is due to the charging and discharging of the cable's parasitic capacitance, caused by the high dv/dt of the PWM voltage pulses.Conversely, as shown in Fig. 17(b), utilizing the ZVS inverter and adopting appropriate parameter selection can almost alleviate the motor overvoltage.Moreover, the motor phase current exhibits reduced current ripple compared with the hardswitching two-level inverter, which can be attributed to the regulated dv/dt and increased rise time of the ZVS inverter.It is also seen that the overvoltage frequency of the reflected wave is 143.6 kHz, which agrees with the calculated reflected wave frequency for a 20 m cable [44] as follows: The mitigation of motor overvoltage is further assessed with Fig. 18, which shows an extended view for a 20 m cable.Upon analyzing the hard-switching two-level motor drive system in Fig. 18(a), it is evident that the maximum motor overvoltage during the rising edge is 1.9 p.u., while during the falling edge it is 1.8 p.u.These results are consistent with the simulated outcomes, which exhibit a peak overvoltage of 1.9 p.u., as shown in Fig. 10(b).In contrast, as seen in Fig. 18(b), the ZVS inverter technique effectively mitigates motor overvoltage.
This behavior can be explained further in Fig. 18(c)-(d), where the motor voltage closely follows the analytical results shown in Fig. 6.The natural rise commutation design, set at 8t p , leads to three intersections between V m,ab and V i,ab .On the other hand, the resonant fall commutation, selected as 4t p , results in a single intersection between V m,ab and V i,ab , as shown in Fig. 6(c).To note, the time difference between V m,ab and V i,ab is the propagation time t p .This is measured at 87 ns, which is in agreement with the calculated value of 86.7 ns for a 20 m cable using (7).

B. Actively Profiling One Type of Commutation
Drawing on previous literature on the ZVS topology [29], regulating the dv/dt of switching transitions can enable active profiling of a specific type of commutation.However, this method is limited to a single type of commutation, and actively profiling one type does not guarantee the profiling of the other two commutations.This limitation is shown in Fig. 19, where only the rising resonant commutations have been actively profiled to 8t p .This results in a motor overvoltage of 2 p.u.
Despite active profiling of one type of commutation, as in the shown example, long-term motor winding damage may still occur since the other two commutations still need to be profiled.The presented motor overvoltage mitigation approach addresses this problem by profiling all three types of commutations.

C. Variations in Load Conditions
It is crucial to consider the effects of motor overvoltage when the rise and fall times deviate from their optimal values.This can occur when there is a substantial reduction in output capacity from rated conditions including variations in load current.Fig. 20 illustrates the change in motor overvoltage for a 20 m cable when compared with deviations in output power from rated conditions.The results show that variations from optimal rise times can increase motor overvoltage more significantly at an output power of 0.6 kW than at 0.2 kW.This is because the rise time increases from 8t p as the output power decreases from rated power.Specifically, at 0.6 kW, the rise time deviates from the optimal rise time, and no dv/dt profiling occurs.At 0.2 kW, the rise time is around 12t p , and thus dv/dt profiling occurs when (8) is met.In contrast, changes in loading conditions have minimal impact on falling resonant commutations, as evidenced by (1).
Despite their influence, alterations in load conditions have a negligible effect on overvoltage, as the maximum overvoltage with the presented method is limited to 1.15 p.u.
Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.

D. Zero-Voltage Switching
The waveforms of V ds and i d during a switching transition in Sector I-I are shown in Fig. 21.It becomes apparent that ZVS is initiated, and the main switch is activated as i d increases, following the clamping of V ds to zero.The decrease in V ds occurs at a rate actively controlled by both the resonant parameters and cable propagation time.This ZVS switching technique results in negligible switching turn-ON losses compared with those incurred by a two-level hard-switching inverter.

VI. CONCLUSION
In SiC MOSFET cable-fed drives, motor overvoltage may arise as a result of high dv/dt.This can lead to substantial strain on cable and motor insulation, resulting from partial discharges and uneven voltage distribution.To alleviate this issue, this article presented a parameter selection strategy of a ZVS SiC-based inverter.
The proposed strategy involves regulating the dv/dt of each resonant and natural commutation to prevent the activation of cable antiresonance and mitigate overvoltage.The method requires carefully selecting resonant parameters based on the length of the cable and cable propagation time.
The performance of the inverter was assessed through theoretical analysis, software simulations, and experiments.In addition, the ZVS inverter was compared with conventional solutions, such as the three-level and two-level inverter, with a passive RC filter.The results indicate that the ZVS inverter has lower losses and exhibits volume advantages.Furthermore, the ZVS inverter can effectively mitigate motor overvoltage, with limited impact when varying motor load conditions due to prolonged rise/fall times.

Fig. 2 .
Fig. 2. Switching current commutation for ZVS legs at positive phase current.(a) Case I. (b) Case II.

Fig. 4 .
Fig. 4. Switching patterns and theoretical waveforms of gate-source voltage V gs , resonant inductor current I Lr , clamping capacitor current I Cc , and drainsource voltage V ds in Sector I-I.Case I commutation is shown in purple, while Case II commutation is shown in red.

Fig. 6 .
Fig. 6.Drive system inverter voltage V i and motor voltage V m at increasing rise times for cable propagation time t p = 65 ns: (a) t p .(b) 2t p .(c) 4t p .(d) 5t p .(Simulation study representing PWM source of varying rise times feeding into 15 m ac cable with the motor-side represented as an open circuit.)

Fig. 7 .
Fig. 7. Guideline procedure for determining the resonant parameters of the ZVS inverter.

Fig. 8 .
Fig. 8. Volume comparison of main components of conventional two-level inverter with a passive LCR and RC filter, Q3L T-type inverter and ZVS inverter.The total volumes of the inverter (including the resonant inductor and capacitance) are correspondingly 1358.45,1282.13,1043.88, and 742.54 cm 3 .These values increase to 1359.7, 1283.4,1046.4,and 743.8 cm 3 when the gate drivers (Texas Instruments ISO5452-Q1) are accounted for.

Fig. 14 .
Fig. 14.Simulated ZVS switching turn-OFF waveforms at different rise times showing the turn-OFF losses P sw,off .(a) Switching waveforms with actively profiled natural fall times for a 5 m cable.(b) Switching waveforms with actively profiled natural fall times for a 20 m cable.

Fig. 17 .
Fig. 17.Differential-mode motor-side voltage V m,ab , inverter-side voltage V i,ab , and two motor phase currents with a cable length of 20 m.(a) Hardswitching two-level inverter.(b) ZVS inverter.

Fig. 18 .
Fig. 18.Differential-mode motor-side voltage V m,ab and inverter-side voltage V i,ab with a cable length of 20 m.(a) Hard-switching two-level inverter.(b) ZVS Inverter.(c) Extended view of ZVS inverter showing natural rise (8t p ).(d) Extended view of ZVS inverter showing resonant fall (4t p ).

Fig. 19 .
Fig. 19.Motor voltage V m,ab when only resonant rise commutation (8t p ) is actively profiled using 20 m cable.

Fig. 20 .
Fig. 20.Measured motor overvoltage for the different types of commutations when output power deviates from rated power using a cable length of 20 m.

Fig. 21 .
Fig. 21.MOSFET V ds and i d during turn-ON switching transients.