Fabrication and performance of 50 nm T-gates for InP high electron mobility transistors

Xin, Cao, Thoms, Stephen, Macintyre, Douglas, McLelland, Helen, Boyd, Euan, Elgaid, Khaled ORCID: https://orcid.org/0000-0003-3265-1097, Hill, Richard, Stanley, Colin R. and Thayne, Iain G. 2004. Fabrication and performance of 50 nm T-gates for InP high electron mobility transistors. Microelectronic Engineering 73-74 , pp. 818-821. 10.1016/S0167-9317(04)00227-8

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Abstract

Fifty nanometre gate length T-gates In0.52A10.48As/In0.53Ga0.47As high electron mobility transistors (HEMTs) on a InP substrate were fabricated with high resolution electron-beam (e-beam) lithography using a novel UVIII/LOR/PMMA T-gate resist stack and with a non-selective digital wet etch gate recess technology. The reproducibility of the gate lithography depends on the substrate slope when mounted on the holder of e-beam lithography tool. This mounting effect is almost eliminated by calibrating the tool using a specially fabricated marker on the wafer instead of the holder marker as in usual. Initial devices exhibited a maximum transconductance (gm) of 950 mS/mm and a current cut-off frequency (ft) of 300 GHz.

Item Type:	Article
Date Type:	Publication
Status:	Published
Schools:	Engineering
Publisher:	Elsevier
ISSN:	0167-9317
Last Modified:	23 Oct 2022 13:03
URI:	https://orca.cardiff.ac.uk/id/eprint/109540

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