A 5-Gb/s 66 dB CMOS variable-gain amplifier with reconfigurable DC-offset cancellation for multi-standard applications

Liu, Zhiqing, Wu, Yunqiu, Zhao, Chenxi, Benedikt, Johannes ORCID: https://orcid.org/0000-0002-9583-2349 and Kang, Kai 2018. A 5-Gb/s 66 dB CMOS variable-gain amplifier with reconfigurable DC-offset cancellation for multi-standard applications. IEEE Access 6 , pp. 54139-54146. 10.1109/ACCESS.2018.2867227

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Abstract

This paper proposes a variable gain amplifier (VGA) with reconfigurable DC-offset cancellation (DCOC) for multi-standard applications. In this design, a cell-based design method and some bandwidth extension technologies are adopted to achieve a high data rate and a wide gain control range simultaneously. In addition, the DCOC having a tunable lower-cutoff frequency can make an optimum compromise between BER and SNR according to the specified baseband standard. The measurements show that the VGA achieves a gain control range from −6 dB to 60 dB, a bandwidth beyond 3 GHz, and a tunable lower-cutoff frequency from 0 to 300 kHz. When entering a 2 23 −1 pseudo-random bit sequence signal at 5 Gb/s, the VGA consumes 17 mW from a 1.2-V supply and the output data peak-to-peak jitter is less than 40 ps. The VGA is fabricated in a 90-nm CMOS process with a chip size (including all pads) of 0.52×0.5 mm 2 .

Item Type:	Article
Date Type:	Published Online
Status:	Published
Schools:	Engineering
Publisher:	Institute of Electrical and Electronics Engineers (IEEE)
ISSN:	2169-3536
Date of First Compliant Deposit:	7 September 2018
Date of Acceptance:	19 August 2018
Last Modified:	05 May 2023 05:36
URI:	https://orca.cardiff.ac.uk/id/eprint/114497

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