MorpheusNet: Resource efficient sleep stage classifier for embedded on-line systems

Kavoosi, Ali, Mitchell, Morgan P., Kariyawasam, Raveen, Fleming, John E., Lewis, Penny ORCID: https://orcid.org/0000-0003-1793-3520, Johansen-Berg, Heidi, Cagnan, Hayriye and Denison, Timothy 2024. MorpheusNet: Resource efficient sleep stage classifier for embedded on-line systems. Presented at: IEEE International Conference on Systems, Man, and Cybernetics (SMC), Honolulu, Oahu, HI, USA, 01-04 October 2023. Proceedings IEEE International Conference on Systems, Man, and Cybernetics (SMC). IEEE, pp. 2315-2320. 10.1109/SMC53992.2023.10394274

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Abstract

Sleep Stage Classification (SSC) is a labor-intensive task, requiring experts to examine hours of electrophysiological recordings for manual classification. This is a limiting factor when it comes to leveraging sleep stages for therapeutic purposes. With increasing affordability and expansion of wearable devices, automating SSC may enable deployment of sleep-based therapies at scale. Deep Learning has gained increasing attention as a potential method to automate this process. Previous research has shown accuracy comparable to manual expert scores. However, previous approaches require sizable amount of memory and computational resources. This constrains the ability to classify in real time and deploy models on the edge. To address this gap, we aim to provide a model capable of predicting sleep stages in real-time, without requiring access to external computational sources (e.g., mobile phone, cloud). The algorithm is power efficient to enable use on embedded battery powered systems. Our compact sleep stage classifier can be deployed on most off-the-shelf microcontrollers (MCU) with constrained hardware settings. This is due to the memory footprint of our approach requiring significantly fewer operations. The model was tested on three publicly available data bases and achieved performance comparable to the state of the art, whilst reducing model complexity by orders of magnitude (up to 280 times smaller compared to state of the art). We further optimized the model with quantization of parameters to 8 bits with only an average drop of 0.95% in accuracy. When implemented in firmware, the quantized model achieves a latency of 1.6 seconds on an Arm Cortex-M4 processor, allowing its use for on-line SSC-based therapies.

Item Type:	Conference or Workshop Item (Paper)
Date Type:	Published Online
Status:	Published
Schools:	Psychology
Publisher:	IEEE
ISBN:	979-8-3503-3702-0
Date of First Compliant Deposit:	5 March 2024
Date of Acceptance:	29 January 2024
Last Modified:	08 Mar 2024 11:47
URI:	https://orca.cardiff.ac.uk/id/eprint/166881

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