Inverse-designed high-efficiency grating couplers with single- and dual-step etching

Han, Shaoshuai, Duan, Shaojing, Yang, Mingxiang, Fang, Kangwei, Dai, Zhifan, Yang, Xin ORCID: https://orcid.org/0000-0002-8429-7598 and Wu, Zhenlin 2026. Inverse-designed high-efficiency grating couplers with single- and dual-step etching. IEEE Photonics Technology Letters 38 (21) , pp. 1487-1490. 10.1109/lpt.2026.3697916

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Abstract

Fabrication-constrained inverse design of high-efficiency grating couplers (GCs) on a 220nm silicon-on-insulator platform is demonstrated using a gradient-assisted optimization framework. By parameterizing 101 geometric degrees of freedom and incorporating a strict 130nm minimum feature size constraint, multi-parameter optimization is achieved with only forward and adjoint simulations per iteration, significantly reducing computational overhead. Compared with conventional forward design, the proposed approach shortens the design cycle by more than fourfold while improving device performance. The fabricated dual-step etched GC, realized in a commercial CMOS process without bottom reflectors or polysilicon overlays, exhibits a measured coupling efficiency of -2.28 dB at 1545.9nm with a 3 dB bandwidth of 40 nm. These results demonstrate that fabrication-aware gradient-assisted optimization enables high-performance, reflector-free silicon grating couplers with strong compatibility for large-scale photonic integration.

Item Type:	Article
Date Type:	Publication
Status:	Published
Schools:	Schools > Engineering
Additional Information:	License information from Publisher: LICENSE 1: URL: https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html, Start Date: 2026-01-01
Publisher:	Institute of Electrical and Electronics Engineers
ISSN:	1041-1135
Last Modified:	02 Jul 2026 13:57
URI:	https://orca.cardiff.ac.uk/id/eprint/187500

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