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Delay matching compensated CMOS microwave frequency doubler

Song, Kyungju, Choi, Heungjae ORCID:, Kim, Chul Dong, Kenney, J. S. and Jeong, Yongchae 2008. Delay matching compensated CMOS microwave frequency doubler. Presented at: 38th European Microwave Conference 2008, Amsterdam, The Netherlands, 27-31 October 2008. 38th European Microwave Conference 2008. Picastaway: IEEE, pp. 464-467. 10.1109/EUMC.2008.4751489

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In this paper, a modified time-delay microwave frequency doubler is proposed. A voltage controlled delay line (VCDL) in the proposed frequency doubler compensates the time-delay mismatching between input and delayed signal. With the delay matching and waveform shaping using adjustable Schmitt triggers, the unwanted fundamental component (f0) and the higher order harmonics such as third and fourth are diminished excellently. In result, only the doubled frequency component (2f0) appears dominantly at the output port. The frequency doubler is designed at 1.15 GHz of f0 and fabricated with TSMC 0.18 mum CMOS process. The measured output power of 2f0 is 2.67 dBm when the input power is 0 dBm. The obtained suppression of f0, 3f0, and 4f0 to 2f0 are 43.65, 38.65 and 35.59 dB, respectively.

Item Type: Conference or Workshop Item (Paper)
Date Type: Publication
Status: Published
Schools: Engineering
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
Publisher: IEEE
ISBN: 9782874870064
Last Modified: 27 Oct 2022 10:08

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