First experimental demonstration of negative capacitance InGaAs MOSFETs with Hf0.5Zr0.5O2 ferroelectric gate stack

Luc, Q. H., Fan-Chiang, C. C., Huynh, S. H., Huang, P., Do, H. B., Ha, M. T. H., Jin, Y. D., Nguyen, T. A., Zhang, K. Y., Wang, H. C., Lin, Y. K., Lin, Y. C., Hu, C., Iwai, H. and Chang, E. Y. 2018. First experimental demonstration of negative capacitance InGaAs MOSFETs with Hf0.5Zr0.5O2 ferroelectric gate stack. Presented at: IEEE Symposium on VLSI Technology, Honolulu, USA, 18-22 Jun 2018. IEEE Symposium on VLSI Technology. Symposium on Vlsi Technology. Piscataway, NJ: IEEE, pp. 47-48. 10.1109/VLSIT.2018.8510644

Full text not available from this repository.

Abstract

We demonstrate, for the first time, the negative capacitance (NC) In 0.53 Ga 0.47 As nMOSFET with 8-nm Hf 0.5 Zr 0.5 O 2 (HZO) as ferroelectric (FE) dielectric for sub-60 mV/dec subthreshold swing (SS). The impact of annealing treatments on the FE properties and electrical characteristics of NC InGaAs nMOSFETs are investigated. Optimized annealing condition results in NC effects at the HZO/Al 2 O 3 /InGaAs nMOSFETs with steep SS property (~ 11 mV/dec).

Item Type:	Conference or Workshop Item (Paper)
Date Type:	Publication
Status:	Published
Schools:	Physics and Astronomy
Publisher:	IEEE
ISBN:	978-1-5386-4218-4
ISSN:	0743-1562
Last Modified:	28 Jul 2020 01:23
URI:	https://orca.cardiff.ac.uk/id/eprint/121858

Citation Data

Cited 3 times in Scopus. View in Scopus. Powered By Scopus® Data

Actions (repository staff only)

Edit Item