Development of an FPGA based time of arrival estimator for PLC applications

Robson, Stephen ORCID: https://orcid.org/0000-0003-3156-1487 and Haddad, A. Manu ORCID: https://orcid.org/0000-0003-4153-6146 2020. Development of an FPGA based time of arrival estimator for PLC applications. Presented at: 55th International Universities Power Engineering Conference (UPEC 2020), Virtual - Torino, Italy, 1-4 September 2020. 2020 55th International Universities Power Engineering Conference (UPEC). IEEE, pp. 1-6. 10.1109/UPEC49904.2020.9209868

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Abstract

This paper details the development of an FPGA-based time of arrival estimator based on the LoRa modulation scheme, targetting deployment on the power line to support smart grid clock dissemination. The algorithm relies on shifting of the received baseband LoRa symbol by small offsets and repeating the demodulation process to find the closest alignment, thus the precise time of arrival. Matlab based simulation results show accuracies in the sub μs range with potential for further enhancement based on statistical averaging of the noise. Hardware efficient FPGA architectures for a transmitter and receiver prototype are shown. The system is realised on a Cyclone V Intel FPGA and initial experimental results show promising performance, though more work is needed to test the algorithm in severe multipath conditions.

Item Type:	Conference or Workshop Item (Paper)
Date Type:	Published Online
Status:	Published
Schools:	Engineering
Publisher:	IEEE
ISBN:	9781728110783
Last Modified:	27 Nov 2022 12:45
URI:	https://orca.cardiff.ac.uk/id/eprint/136577

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