Design of a phase disposition PWM technique for reduced switch asymmetric 31-level inverter

Khan, Muhammad Yasir Ali, Liu, Haoming, Alhani, Emad and Karim, Hamid 2021. Design of a phase disposition PWM technique for reduced switch asymmetric 31-level inverter. Presented at: 2021 International Conference on Computing, Electronic and Electrical Engineering (ICE Cube), Quetta, Pakistan, 26-27 October 2021. Quetta, Pakistan. IEEE, pp. 1-10. 10.1109/ICECube53880.2021.9628332

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Abstract

A challenging task in designing a multi-level inverter is to increase the output voltage level while keep the switching devices, DC voltage sources, and corresponding diodes to a minimum number. In this paper, the analysis, and implementation of a 31-level asymmetric inverter is presented. This shows efficient performance in terms of voltage levels, number of components count, and total harmonic distortion, compared to conventional topologies. As a result of this, the filter circuit’s size, cost, and complexity are considerably reduced. A modified sinusoidal pulse width modulator with a multicarrier phase disposition scheme is used to generate gate signals for 31-levels voltage at the output side. The modeling and analysis of the proposed MLI and PWM topology is conducted in Simulink environment, while hardware results authenticated the performance.

Item Type:	Conference or Workshop Item (Paper)
Date Type:	Published Online
Status:	Published
Schools:	Engineering
Publisher:	IEEE
ISBN:	9781665401548
Last Modified:	22 Feb 2022 15:00
URI:	https://orca.cardiff.ac.uk/id/eprint/147440

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