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Lateral tunnel epitaxy of GaAs in lithographically defined cavities on 220 nm silicon-on-insulator

Yan, Zhao, Ratiu, Bogdan-Petrin, Zhang, Weiwei, Abouzaid, Oumaima, Ebert, Martin, Reed, Graham T., Thomson, David J. and Li, Qiang ORCID: 2023. Lateral tunnel epitaxy of GaAs in lithographically defined cavities on 220 nm silicon-on-insulator. Crystal Growth and Design 23 (11) , pp. 7821-7828. 10.1021/acs.cgd.3c00633

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Current heterogeneous Si photonics usually bond III–V wafers/dies on a silicon-on-insulator (SOI) substrate in a back-end process, whereas monolithic integration by direct epitaxy could benefit from a front-end process where III–V materials are grown prior to the fabrication of passive optical circuits. Here we demonstrate a front-end-of-line (FEOL) processing and epitaxy approach on Si photonics 220 nm (001) SOI wafers to enable positioning dislocation-free GaAs layers in lithographically defined cavities right on top of the buried oxide layer. Thanks to the defect confinement in lateral growth, threading dislocations generated from the III–V/Si interface are effectively trapped within ∼250 nm of the Si surface. This demonstrates the potential of in-plane co-integration of III–Vs with Si on mainstream 220 nm SOI platform without relying on thick, defective buffer layers. The challenges associated with planar defects and coalescence into larger membranes for the integration of on-chip optical devices are also discussed.

Item Type: Article
Date Type: Publication
Status: Published
Schools: Physics and Astronomy
Publisher: American Chemical Society
ISSN: 1528-7483
Funders: EPSRC
Date of First Compliant Deposit: 12 October 2023
Date of Acceptance: 26 September 2023
Last Modified: 04 Jul 2024 01:05

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