Effective InAsP dislocation filtering layers for InP heteroepitaxy on CMOS-standard (001) silicon

Liu, Shangfeng, Ratiu, Bogdan-Petrin, Jia, Hui, Yan, Zhao, Wong, Ka Ming, Martin, Mickael, Tang, Mingchu, Baron, Thierry, Liu, Huiyun and Li, Qiang ORCID: https://orcid.org/0000-0002-5257-7704 2024. Effective InAsP dislocation filtering layers for InP heteroepitaxy on CMOS-standard (001) silicon. Applied Physics Letters 125 (8) , 082102. 10.1063/5.0219507

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Abstract

In this work, we report InAsP-based dislocation filter layers (DFLs) for InP heteroepitaxy on CMOS-standard (001) Si substrates, demonstrating a threading dislocation density of 3.7 × 107 cm−2. The strain introduced by InAsP induces dislocation bending at the InAsP/InP interface, thereby facilitating the reaction and annihilation of dislocations during their lateral glide. Concurrently, the InP spacer exhibits tensile strain, leading to the formation of stacking faults (SFs). With a comprehensive analysis utilizing x-ray diffraction, electron channeling contrast imaging, and transmission electron microscopy, the effects of DFL-induced strain on dislocations and SFs are investigated. Fine-tuning the strain conditions allowed low-dislocation-density while SF-suppressed, anti-phase boundary free InP on Si. This work, therefore, provides a useful buffer engineering scheme for monolithic integration of InP-based electronic and photonic devices onto the industry-standard silicon platform.

Item Type:	Article
Date Type:	Published Online
Status:	Published
Schools:	Physics and Astronomy
Publisher:	American Institute of Physics
ISSN:	0003-6951
Funders:	EPSRC
Date of First Compliant Deposit:	20 August 2024
Date of Acceptance:	8 August 2024
Last Modified:	21 Aug 2024 13:00
URI:	https://orca.cardiff.ac.uk/id/eprint/171505

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