Towards an energy consumption optimisation framework in selective laser sintering system: Leveraging deep learning and FPGA technologies

Li, Yixin, Ryan, Michael ORCID: https://orcid.org/0000-0002-8104-0121, Robson, Stephen ORCID: https://orcid.org/0000-0003-3156-1487 and Liu, Ying ORCID: https://orcid.org/0000-0001-9319-5940 2025. Towards an energy consumption optimisation framework in selective laser sintering system: Leveraging deep learning and FPGA technologies. Presented at: 4th ICPR AEM Poznań 2024, Poznan, Poland, 28 June - 3 July 2024. Implementation of Circular Economy in Supply Chains and Production Systems. EcoProduction Cham, Switzerland: Springer, pp. 39-52. 10.1007/978-3-031-88926-4_3

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Abstract

The additive manufacturing paradigm offers unique advantages in terms of customisation and flexibility while consuming considerable energy. As a critical factor affecting energy consumption, Convolutional Neural Networks (CNNs) extract deep features from sliced models. This paper utilises a combination of Deep Learning (DL) and Field-Programmable Gate Array (FPGA) technology to predict energy consumption despite the computationally expensive nature of CNN-based approaches. The combination of the task-specific model and prevailing CNN architecture is necessary to optimise the extraction of image features and learning efficiency. Furthermore, knowledge distillation (KD) is accomplished by pooling fused features based on feature pyramid networks and generating a compact and simple CNN by distilling knowledge on layer-wise features. After further quantisation, a compact CNN is deployed on FPGA platforms for feature extraction at the edge to analyse energy consumption. In the CNN model using multi-scale features, when feature-based KD is applied, the size of the student network is reduced without compromising as evidenced by a decrease in the RMSE from 3.71 Wh/g to 3.63 Wh/g (a decrease of about 2.16 %) a decrease in the MAE from 2.9 Wh/g to 2.81 Wh/g ( decreased by about 3.10%), while the MCC decreased from 0.81 to 0.75 (decreased by about 7.41%). The on-chip power consumption reaches approximately 0.339 W, including dynamic and static consumption, with intermediate-level resource utilisation.

Item Type:	Conference or Workshop Item - published (Paper)
Date Type:	Publication
Status:	Published
Schools:	Schools > Engineering
Publisher:	Springer
ISBN:	978-3-031-88925-7
Last Modified:	28 Apr 2026 14:06
URI:	https://orca.cardiff.ac.uk/id/eprint/172281

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