Design and development of an FPGA-based lock-in amplifier for high-frequency earthing measurements

Meads, Oscar, Priddle, James, Pushpanathan, Dhanyeshver, Clark, David ORCID: https://orcid.org/0000-0002-1090-2361, Albano, Mauizio, De Araujo, Anderson Justo, Robson, Stephen ORCID: https://orcid.org/0000-0003-3156-1487 and Haddad, A. Manu ORCID: https://orcid.org/0000-0003-4153-6146 2025. Design and development of an FPGA-based lock-in amplifier for high-frequency earthing measurements. Presented at: UPEC 2025, London, UK, 02-05 September 2025. 2025 60th International Universities Power Engineering Conference (UPEC). IEEE, 10.1109/upec65436.2025.11279753

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Abstract

This paper presents an FPGA-based digital lock-in amplifier designed for high-frequency earthing impedance measurements. The primary motivation is to enable a portable, field-deployable measurement system capable of high frequency measurements in harsh conditions. The implementation features an efficient recursive low-pass filter and supports user-configurable parameters, including frequency and averaging time. Laboratory and outdoor field tests on a driven rod electrode demonstrate good comparative performance across a 10–100 kHz bandwidth.

Item Type:	Conference or Workshop Item (Paper)
Date Type:	Published Online
Status:	In Press
Schools:	Schools > Engineering
Publisher:	IEEE
ISBN:	979-8-3315-6520-6
Last Modified:	05 Jan 2026 16:48
URI:	https://orca.cardiff.ac.uk/id/eprint/183561

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