Logarithmic number system and floating-point implementations of a well-conditioned RLS estimated algorithm on FPGA

Lee, B. and Lever, Kenneth Vincent 2003. Logarithmic number system and floating-point implementations of a well-conditioned RLS estimated algorithm on FPGA. Presented at: 37th Asilomar Conference on Signals, Systems and Computers, Monterey, USA,

Full text not available from this repository.

Item Type:	Conference or Workshop Item (Paper)
Schools:	Engineering
Last Modified:	24 Jun 2017 08:48
URI:	https://orca.cardiff.ac.uk/id/eprint/21044

Actions (repository staff only)

Edit Item