(Invited) Technology options to reduce contact resistance in Nanoscale III-V MOSFETs

Lee, R. T. P., Loh, W. Y., Tieckelmann, R., Orzali, Tommaso ORCID: https://orcid.org/0000-0001-9446-5789, Huffman, C., Vert, A., Huang, G., Kelman, M., Karim, Z., Hobbs, C., Hill, R. J. W. and Papa Rao, S. S. 2015. (Invited) Technology options to reduce contact resistance in Nanoscale III-V MOSFETs. ECS Transactions 66 (4) , pp. 125-134. 10.1149/06604.0125ecst

Full text not available from this repository.

Abstract

III-V semiconductors have emerged as the leading candidate to replace Si as the n-FET channel material for future low power logic applications. However, to realize the full performance benefits of III-V channels, it is crucial that external parasitic resistance (Rext) be minimized. Among the different components of Rext, contact resistance (RC), between metal and source/drain (S/D) junctions, has become the critical focus. Historically, multi-layered Au-based contacts (e.g. Au/Ge/III-V) are used in III-V processing to lower RC. However, the renewed interest in III-V semiconductors has attracted an increasing interest in developing Au-free contacts to III-V with low RC. In addition, a “silicide-like” metal contact process for III-V was recently developed by reacting Ni with InGaAs to form Ni-InGaAs. This is significant as it enables self-alignment and offers the option of using a common S/D contact metal in a hetero-integrated device flow (e.g. Ge/III-V). In this paper, we will review these RC reduction options and present some of our recent results on contact/junction engineering to lower RC in III-V MOSFETs.

Item Type:	Article
Date Type:	Published Online
Status:	Published
Schools:	Physics and Astronomy
Publisher:	Electrochemical Society
ISSN:	1938-5862
Last Modified:	01 Nov 2022 11:15
URI:	https://orca.cardiff.ac.uk/id/eprint/94351

Citation Data

Cited 6 times in Scopus. View in Scopus. Powered By Scopus® Data

Actions (repository staff only)

Edit Item