Backside and edge cleaning of III–V on Si wafers for contamination free manufacturing

Vert, Alexey, Orzali, Tommaso ORCID: https://orcid.org/0000-0001-9446-5789, Dyer, Tom, Hill, Richard, Satyavolu, PapaRao, Barth, Edward, Gaylord, Richard, Hu, Shan, Vivekanand, Saikumar, Herman, Joshua, Rana, Uzma and Kaushik, Vidya 2015. Backside and edge cleaning of III–V on Si wafers for contamination free manufacturing. Presented at: Advanced Semiconductor Manufacturing Conference (ASMC), Saratoga Springs, NY, 3-6 May 2015. Advanced Semiconductor Manufacturing Conference (ASMC), 2015 26th Annual SEMI. New York: Institute of Electrical and Electronics Engineers (IEEE), pp. 362-366. 10.1109/ASMC.2015.7164420

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Abstract

III-V on Silicon epitaxial wafers are typically contaminated with residual III-V materials on the backside, bevel and front side exclusion zone. This contamination poses a risk for device manufacturing. The level of contamination can vary from trace to gross, depending on the epitaxial deposition process and method of backside wafer surface protection. Even when the backside surface is well protected and cleaned, trace amounts of III-V material including arsenic can still be detected. Wet clean methods usually use acid chemistries and if not optimized may involve significant chemical cost, safety risks, and contamination issues. Wafer backside and edge cleaning processes, employed to remove residual III-V material need to be designed for robust performance with a wide range of deposited materials and repeatable results in order to ensure contamination free manufacturing at subsequent steps of the fabrication flow.

Item Type:	Conference or Workshop Item (Paper)
Date Type:	Published Online
Status:	Published
Schools:	Physics and Astronomy
Uncontrolled Keywords:	Contamination Free Manufacturing, III-V Materials, Backside Cleaning
Publisher:	Institute of Electrical and Electronics Engineers (IEEE)
ISBN:	9781479999309
Last Modified:	01 Nov 2022 11:15
URI:	https://orca.cardiff.ac.uk/id/eprint/94350

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