Zaidi, Z. H., Lee, K. B., Roberts, J. W., Guiney, I., Qian, H., Jiang, S., Cheong, J. S., Li, P., Wallis, D. J. ![]() |
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Abstract
In a bid to understand the commonly observed hysteresis in the threshold voltage (VTH) in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors during forward gate bias stress, we have analyzed a series of measurements on devices with no surface treatment and with two different plasma treatments before the in-situ Al2O3 deposition. The observed changes between samples were quasi-equilibrium VTH, forward bias related VTH hysteresis, and electrical response to reverse bias stress. To explain these effects, a disorder induced gap state model, combined with a discrete level donor, at the dielectric/semiconductor interface was employed. Technology Computer-Aided Design modeling demonstrated the possible differences in the interface state distributions that could give a consistent explanation for the observations.
Item Type: | Article |
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Date Type: | Published Online |
Status: | Published |
Schools: | Engineering |
Publisher: | AIP Publishing |
ISSN: | 0021-8979 |
Date of First Compliant Deposit: | 16 May 2018 |
Date of Acceptance: | 14 May 2018 |
Last Modified: | 27 Nov 2024 22:45 |
URI: | https://orca.cardiff.ac.uk/id/eprint/111500 |
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